Asynchronous Bypass Channel Routers

Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. Typically, these systems require fully balanced clock distribution trees to enable synchronous communication between all nodes on-chip, resulting in higher power consumption. One approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) mesochronous clocking scheme. NoCs implemented with a GALS clocking scheme, however, tend to have high latencies as packets must be synchronized at every hop between source and destination. In this paper, we propose a novel router microarchitecture for GALS NoCs which offers superior performance versus typical synchronizing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology that leverages the advantages of the bypass channel offered by our router design. Our experiments show that our design improves the performance of a conventional synchronizing design with similar resources by up to 26% at low loads and increases saturation throughput by up to 11%.